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CV Digital Design Engineer / ASIC | |
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Je suis un Digital Designer et j'habite à Nice. Je suis expérimenté dans le conception RTL développement de Front-End ASIC, avec expérience dans le développement de système avec Micro ARM et dans le développement d'architectures DSP, IPs, IC en général.
Actuellement, je suis libre de commencer immédiatement.
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Digital HW Design Engineer
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Connaissances techniques
-Langages : HDL for RTL and Test Bench:
VHDL (mainly), Verilog
-Environnement et systèmes : Unix-Linux, Windows
-Logiciels particuliers :
Main SYNOPSYS and CADENCE design tools for synthesis, simulation and verification:
Design Compiler (Chip Synthesis)
Physical Compiler (Cell Placement)
Formality (Formal Verification)
Primetime (STA)
TetraMAX (ATPG – Patterns Generation)
VSS (Simulation)
NC-Sim
Fpga development : Quartus
SOPC
NIOS
Assembly
Matlab
Main Windows Software as Office (Word, Excel, PowerPoint)
-Autres :
Formal training for:
Architecture of Integrated System, Pipelining
DSP Architecture & Micro, Risc and VLIW
Cache Architecture, Chip Synthesis
I worked for eight years as:
- DSP & Micro Architecture development Design Engineer
- ARM, Asic, IP/Macro Design Engineer
Other:
- BIST (insertion - optimization)
- AMBA (AHB, APB)
- Asynchronous / Synchronous – Single / Multi Clocks domains
- CMOS Technology used: up to 65nm for IC and 90nm for a project on Fpga
Langues
- Italien : Mother tongue
- Anglais : Advanced knowledge in writing and speaking
- Français: Medium in speaking
Expérience professionnelle
Jusqu’à aujourd’hui :
Bien que sans emploi, j\'ai approfondi mes connaissances techniques travaillant à la maison avec des logiciels pour la conception, synthèse et simulation des certains systèmes et périphériques que j’ai développé moi-même:
• Implémentation en VHDL d’un Contrôleur pour mémoire SDRAM - DDR2 1Gb
• Etude et implémentation du Data-Link-Layer (DLL) pour le Protocole PPP sur Ethernet (PPPoE) selon RFC-2516, étude compromis sur la réalisation des parties Sw/Hw
- Implémentation du système en Vhdl
-Synthèse avec Quartus (Altera)
-Simulation avec Modelsim
• Conception et implémentation d’un SERDES adapté pour un bus type AMBA (Burst-Transfer, Little-Big Endian, différent Master-Slave Data-Size Casting, FIFO)
-Implémentation du système en Vhdl
-Synthèse avec Quartus (Altera)
-Simulation avec Modelsim
De février 2007 à avril 2008
ASTEK Consultant
Consultant for the ASTEK Company in Sophia-Antipolis (France),
as Cadre :
Titre du poste : Digital HW Design Engineer
Mission as ASTEK Consultant:
De février 2007 à juin 2007
NXP-PHILIPS
Emplacement: Sophia-Antipolis (France)
Titre du poste : Digital HW Design Engineer
Contexte du projet : Implementation of a Bluetooth Digital Receiver block on FPGA
In order to use a new different architecture for a Bluetooth digital receiver my job has been to understand the old architecture then to modify the RTL to implement the new one, spec given. Moreover, I designed new sub-blocks, in particular the Clocks-Generation to obtain reduction in Power Consumption as well as a new DBUS Control Interface.
After the RTL development, in order to test the functionality and performance of this new architecture, I brought about some other modifications for the only Fpga implementation.
I wrote test benches to simulate the top level and synthesized a netlist for the Altera Fpga. Then a board environment has been created in Laboratory to verify the functionality of the project on Fpga.
I completed my job writing a User Manual and a Release Document.
De 2000 à 2007
STMICROLECTRONICS
Emplacement: Milan (Italy)
Titre du poste : Experienced Digital HW Design Engineer for ASIC development
Projets :
In 2000, I started working for STMicroelectronics in order to broaden my knowledge and experience in Processor Microarchitectures
-2007, march-2006
Terminated the collaboration with the STMicroelectronics I started my researches to work abroad. I had some contacts with European companies but without arriving to sign a contract.
During last months in 2006 I thought to start an own private work as freelance in Italy.
After, for private chosen, I concentrated my job research in France.
-2006
Since dec 2005 to feb 2006 I worked in STM in a group in order to design and develop new platforms with external brand (not STM) DSPs
-2005-2004
Responsible for ARM-L210 2°level Cache Controller for a micro-dsp platform for multimedia application: the Nomadik STM project.
-Customization, optimization, achievement and verification of an IP/macro including:
Arm926 - L210ctrl - Cache - Bist , following NOKIA’s specifics for mobile phones
-Customization, optimization, achievement and verification of different IP/macros including:
A7s - L210ctrl - Cache – Bist , following other customers specifications.
-I made, furthermore, same BIST architecture improvements.
Technology: Cmos H9 and H10
-RTL(Vhdl) Macro development
-RTL Simulation: NC-Sim
-Synthesis (with internal Clock_Gating): Design_Compiler and Physical_Compiler
-Scan Chains insertion, ATPG coverage: Tetramax
-Formal Verification: Formality
-Gate-Level Simulation: NC-Sim
-2003
Responsible for the ARML210 2° level Cache Controller
Responsible for the macro implementations of the ARM Microcontrollers ARM926ejs and ARM946es.
-I brought architectural improvements in order to speed up the BISTs paths between caches and core.
-I developed some Macros for different customers including: ARM Micro - Cache - Bist
Technology: Cmos H9
-RTL(Vhdl) Macro development
-RTL Simulation: NC-Sim
-Synthesis (with internal Clock_Gating): Design_Compiler and Physical_Compiler
-Scan Chains insertion, ATPG coverage: Tetramax
-Formal Verification: Formality
-Gate-Level Simulation: NC-Sim
-STA: Primetime
Responsible for the STM DSP Emerald:
-Development of sub_blocks : Parallel_to_Serial - Sync - Rx FIFO controller - registers bank - Serial Master interface
-Development of a Macro for a Smart Sensor Device including:
DSP - Sram single & dual port - the sub_blocks above.
Test Bench and simulation.
-2002-2001
Responsible for the macro implementations of the ARM microcontroller A7tdmi-s to customize and achieve some customer specific IP/macros.
Responsible for the STM DSP Emerald HW
-Microarchitecture development: improvements and new features - Data Path, Alu, Stack, New Instructions -
-I realized an FFT Coprocessor for the DSP.
-Peripherals design.
In charge to interact with customers and for the macro implementations.
Technology: Cmos H8 and H9
-RTL(Vhdl) Macro development
-RTL Simulation: NC-Sim
-Synthesis (with internal Clock_Gating): Design_Compiler and Physical_Compiler
-Scan Chains insertion, ATPG coverage: Tetramax
-Formal Verification: Formality
-Gate-Level Simulation: NC-Sim
-STA: Primetime
-2000
I began working for STM as a Digital DSP ASIC designer.
With a solid knowledge of VHDL design, I became involved in a group which develops RTL for IP.
Started on-the-job training specifically on synthesis and verifications of the DSP and some peripherals as:
Event Counter, Frequency Capture, Timers, GpIO, Serial&Parallel IO, Interrupt Controller, Motor Control, Watchdog, Wrapper, Mailbox
in order to develop a demonstrative Chip.
Etudes
-Lieu : Federico II University of Naples (Italy) année : March, 1998
-diplôme : Bac+5 : Degree in Electronic Engineering, specialization in Microelectronics Vote: 110/110 cum Laude
- August 1996 to July 1997 :
Military Service in Aviation at the Air Force Academy in Pozzuoli, Naples (Italy)
-Lieu : F. Giordani ITIS School of Naples (Italy) année : June, 1987
- diplôme : Bac : “Informatica” (Computer Science)
Vote: 45/60
Autres expériences:
1998-2000: After the degree and the military service I wanted to continue the University carrier to become a researcher then a teacher. I had some offers for PhD after the thesis. I decided in meanwhile to contact Companies for a work as designer for Asic and Dsp.
1987-1996: After the Diploma of high school, in parallel with the University studies I tried to use my Software knowledge in order to develop programs, but without enter in contact with Company for real work contracts.
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| Recherche d'Emploi : | Recherche Active d'emploi | |
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| Formation : | Bac+6 | |
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| Expérience : | 6 à 10 ans | |
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| Résidence : | Alpes-Maritimes (06) | |
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| Préférences Géographiques : |
Alpes-Maritimes (06) - Bouches-du-Rhône (13) | |
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| Mots Clefs : | ASIC, SoC, RTL, VHDL, Front-End, Fpga, Altera, Quartus, SOPC, ingénieur, numérique, Verilog, IC, Embedded System, développeur, AMBA, AHB, DSP, Micro, Risc, ARM | |
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