I am an Italian PhD Electronic Engineer, 10 years experienced, currently employed in Germany as FPGA Design Engineer for the EADS GmbH.
As you will see from my resume, I possess a wealth of experience for:
• VHDL programming for state of art FPGAs (Stratix, Virtex), following the whole FPGA development, from specifications to testing.
• Signal processing analysis for space telecommunications and for radar applications (with extensive Matlab/Simulink/C++ simulations).
• DSP programming (both C and Assembler).
Academically, I achieved a first class Cum Laude degree in Electronics, with a subsequent PhD in Space Systems and Technology.
Should you require any further information, please do not hesitate to contact me. | |
Date and place of birth: 3 December 1972, Rome (Italy)
Nationality and marital status: Italian, unmarried
WORK EXPERIENCES
July 2008–Today: Working for EADS GmbH (Ulm, Germany), global leader in aerospace, defence and related services. Radar Signal Processing Division. Permanent contract, gross annual salary 65000 euro.
Design, simulation and testing of digital circuits implemented on state of art FPGAs (Stratix, Cyclone), VHDL and C programming, use of advanced tools for digital design (ModelSim, SOPC Builder, Nios II EDS, Quartus II). Main interests: Systems on a Chip with Altera Nios II, Ethernet and RAM/ROM adaptors, controllers, VME interfacing, UARTs, 8b/10b encoding, HOTLink SerDes, FIR/IIR/FFT filtering.
September 2001–July 2008: Working for Space Engineering S.p.A. (Rome), a company operating in satellite telecommunications, Signal Processing Division.
Design, simulation and testing of digital circuits implemented on state of art FPGAs, VHDL and C/C++ programming, use of advanced tools for digital design (ModelSim, Precision RTL, Quartus II, ISE). Main interests: complete CDMA modems for military sat-ellites, high speed up–down sampling and up–down conversion, multirate FIR/IIR filter-ing, phase noise generation, controllors, interfaces, Matlab/Simulink/C++ simulations of signal processing issues for space telecommunications. Involved in several international projects led by ESA (European Space Agency), Alenia Spazio (Italian company specialized in satellite environment) and ASI (Italian Space Agency).
Very good knowledge of test and measurement equipment such as oscilloscopes, logic analyzers, spectrum analyzers and signal generators.
January 2000–September 2001: Worked for Alenia Marconi Systems S.p.A. (Rome), the main Italian radar company, Radar Signal Processing Division.
Acquired good knowledge of DSP–based systems and multiprocessor VME boards. Assembler programming of the 21060 SHARC DSP, assembler and C coding of radar algo-rithms, Matlab simulations of radar issues, FFT pulse compression filtering. Attended an 80 hours course on Radar and an 8 weeks course on telecommunications networks (SDH, ATM, X.25, ISDN, TCP/IP, LAN).
EDUCATION
November 2005–November 2008: “Tor Vergata” University (Rome). PhD Degree in Space Systems and Technology (Digital Electronics Department). The PhD activity has been developed while I was working at Space Engineering S.p.A.
Title of the thesis: “Implementation of iterative multiuser joint detection techniques in a DVB-RCS satellite scenario”.
November 1991–April 1999: “Tor Vergata” University (Rome). Degree in Electronic En-gineering cum laude (graduation mark 100 cum laude out of 100, first class honours). During the last year, I also carried out my national service (compulsory at that time).
Title of the thesis: “Development of an OFDM modem for transmitting digital infor-mation over powerlines”.
1986–1991: “Enrico Fermi” High School, Frascati (Rome). Diploma in Electronics (graduation mark 60 out of 60, first class honours). Main subjects: Analog and Digital Elec-tronics, Telecommunications.
LANGUAGES
Italian (Mother tongue)
English (Very good written and spoken)
German (Basic)
PROGRAMMING LANGUAGES AND SOFTWARE TOOLS
VHDL (Expert)
Assembler (Z80, TMS320C50, Sharc 21060) (Very good)
C/C++ (Very good)
Matlab/Simulink (Very good)
ModelSim (Expert)
LeonardoSpectrum / Precision RTL (Expert)
Quartus II / SOPC Builder / Nios II EDS (Altera) (Expert)
ISE (Xilinx) (Good)
VisualDSP++ (Analog Devices) (Fair)
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